Assessing the interconnect reliability, stress and deformation around via in flip chips

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dc.contributor.author Juma, Mary A.
dc.contributor.author Xuliang, Zhang
dc.date.accessioned 2022-01-13T12:01:41Z
dc.date.available 2022-01-13T12:01:41Z
dc.date.issued 2014-09
dc.identifier.citation International Conference on Control Engineering and Electronics EngineeringVolume: 95 en_US
dc.identifier.uri https://www.researchgate.net/publication/271437602_Assessing_the_interconnect_reliability_stress_and_deformation_around_via_in_flip_chips
dc.identifier.uri http://repository.seku.ac.ke/handle/123456789/6686
dc.description.abstract Analysis System (ANSYS) Tutorial, two dimensional (2D) fracture analysis release 14.0 helped us develop new ideas about stress development and deformation around via in flip chips. The chips are from five different materials namely; silicon, copper, aluminum, silicon nitride and polyamide. They are rectangular plates each 1m × 0.4m but because of symmetry only a quadrant is used in simulation and central holes around via of diameter 0.2m each. Each plate is subjected to a normal stress of -1N/m2. These values were used for easy computational purposes. Silicon material was also assumed to be isotropic. An analysis system; graphical user interface (GUI) was used in the computation of the displacements, maximum and minimum stresses. From the results we noted that different materials have different displacements and stress levels. en_US
dc.language.iso en en_US
dc.title Assessing the interconnect reliability, stress and deformation around via in flip chips en_US
dc.type Presentation en_US


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