Assessing cracks and interconnect reliability in flipchips

Abstract

One of the most common forms of failures observed in flipchips brittle thin films subjected to stress is cracking. The crack growth rate depends on intrinsic film properties, stress and some environmental factors. In part 1 of this paper, we investigate central crack on different material planes. The planes are made from silicon, copper, aluminum, polyamide and silicon nitride. Each plane is 1.0m x 0.4m and has a crack length of 0.04m. Because of symmetry only 0.5m and o.2m of the plate is used. They are subjected to a normal stress of 100MPa. A 2D FEA model is developed and ANSYS software is used to calculate the MODE I Stress Intensity Factor (SIF) on each material plane. The SIF of the materials are compared and a result is arrived at which creates room for recommendation. In part 2, the same material types and sizes are used but with central holes of diameter 0.2m each. Each plate is subjected to a normal stress of -1N/m2. Ansys, GUI was used in the computation of the displacements, maximum and minimum stresses. From the results we noted that different materials have different displacements and stress levels.